A wafer burn-in test methodology can be used to verify the reliability of an integrated circuit memory device. In accordance with a wafer burn-in test, a voltage higher than a normal operational voltage for the integrated circuit memory device is applied at a high temperature (i.e., stress is applied) to test for the presence of various defects that may be exhibited while the integrated circuit memory device is still in the wafer state. Thus, an integrated circuit memory device may include test circuits for performing wafer burn-in tests.
In particular, a conventional wafer burn-in test may involve the selection of odd-numbered word lines or even-numbered word lines and then the application of stress to write data into the memory cells. Alternatively, a conventional wafer burn-in test may involve the selection of word lines corresponding to true cells or complementary cells and then the application of stress to write data into these memory cells. A conventional wafer burn-in test may also include a read operation in which all word lines are selected and stress is applied to read data from the memory cells.
FIG. 1 is a block diagram of a conventional integrated circuit memory device having a wafer burn-in test capability. With reference to FIG. 1, the integrated circuit memory device includes a memory cell array 101, a wafer burn-in enable signal generation unit 103, a word line selection unit 105, a write and read control unit 107, and a sense amplifier control unit 109. The word line selection unit 105 includes a control signal generation unit 105a, an address decoding unit 105b, and a word line enable unit 105c. The internal architectures of the aforementioned components are shown in detail in FIGS. 2-5. In particular, FIG. 2 is a circuit diagram of the wafer burn-in enable signal generation unit 103 of FIG. 1. FIGS. 3 and 4 are circuit diagrams of the control signal generation unit 105a of FIG. 1 and the address decoding unit 105b of FIG. 1 respectively. And FIG. 5 is a circuit diagram of the write and read control unit 107 of FIG. 1. In addition, FIG. 12 illustrates internal circuitry of the memory cell array 101. The internal details of these circuits are well known to those having skill in the art and need not be described further.
With reference to FIGS. 1-5 and 12, operations of a conventional integrated circuit memory device having a wafer burn-in test capability will be described hereafter. When a signal exhibiting a "high" logic value is applied to a pin WBE during a wafer burn-in test, the wafer burn-in enable signal generation unit 103 drives a wafer burn-in enable signal PWBE to a "high" logic value (see FIG. 2). While the wafer burn-in enable signal PWBE is driven "high," the word line selection unit 105 can selectively activate a plurality of word lines WL0 through WLn of the memory cell array 101 in response to signals applied to the four pins A0, A1, A2, and A3. More specifically, the control signal generation unit 105a generates control signals PWBE0B through PWBE3B, which correspond to the signals applied to the four pins A0, A1, A2, and A3 (see FIG. 3). In response to the control signals PWBE0B through PWBE3B, the address decoding unit 105b activates address signals selected from the address signals RA0B1B through RA01, which correspond to the word lines WL0 through WLn of the memory cell array 101. The word line enable unit 105c activates word lines selected from the word lines WL0 through WLn of the memory cell array 101 in response to the address signals RA0B1B through RAij. Inasmuch as the wafer burn-in enable signal PWBE is "high," the address signals RAiBjB through RAij, where i, j=2, 3, . . . , (i.noteq.j) are driven to a "high" logic value.
For example, the following patterns of input signals can be applied to the control signal generation unit 105a to select various combinations of word lines for a wafer burn-in test. To activate even-numbered word lines selected from the word lines WL0 through WLn of the memory cell array 101, the pattern (1, 0, 1, 0) is applied to the four pins A0, A1, A2, and A3. As a result, the control signals PWBE0B through PWBE3B become (0, 1, 0, 1) so that the address signals RA0B1B through RA01 become (1, 0, 1, 0). To activate odd-numbered word lines selected from the word lines WL0 through WLn of the memory cell array 101, the pattern (0, 1, 0, 1) is applied to the four pins A0, A1, A2, and A3. As a result, the control signals PWBE0B through PWBE3B become (1, 0, 1, 0) so that the address signals RA0B1B through RA01 become (0, 1, 0, 1). To activate all of the word lines WL0 through WLn of the memory cell array 101, the pattern (1, 1, 1, 1) is applied to the four pins A0, A1, A2, and A3. As a result, the control signals PWBE0B through PWBE3B become (0, 0, 0, 0) so that the address signals RA0B1B through RA01 become (1, 1, 1, 1).
Thus, to activate either odd-numbered or even-numbered word lines selected from the word lines WL0 through WLn of the memory cell array 101 for a wafer burn-in test involving a write operation, two of the control signals PWBE0B through PWBE3B are driven to a "high" logic value. In addition, an output signal PEQiB (i.e., an operation control signal or equalization signal) of the write and read control unit 107 is also driven to a "high" logic value. Thus, referring now to FIG. 12, the equalization transistors 1203a, 1203b, and 1203c for equalizing a predetermined bit line pair of the memory cell array 101 are turned on and a voltage level VBL is written into a predetermined memory cell through the equalization transistors 1203a, 1204b, and 1203c.
To activate all of the word lines WL0 through WLn of the memory cell array 101 for a wafer burn-in test involving a write operation (i.e., to perform the write operation with respect to all memory cells), the control signals PWBE0B through PWBE3B are driven to a "low" logic value. Accordingly, the output signal PEQiB of the write and read control unit 107 is also driven to a "low" logic value (see FIG. 5). As a result, the equalization transistors 1203a, 1203b, and 1203c of FIG. 12 are turned off, which prevents the write operation from being performed on all of the memory cells.
To perform a wafer burn-in test involving a read operation, a signal exhibiting a "high" logic value is applied to a pin A4. In response thereto, the sense amplifier control unit 109 drives a sense amplifier enable signal PSE to a "high" logic value so that the sense amplifier of the memory cell array 101 (see, e.g., FIG. 12, sense amplifiers 1207 and 1211) is enabled to allow the read operation. In a conventional integrated circuit memory device having a wafer burn-in test capability, all of the word lines of the memory cell array 101 are typically activated to perform the read operation with respect to all memory cells. In other words, when a wafer burn-in test involving a read operation is performed, the pattern (1, 1, 1, 1) is applied to the four pins A0, A1, A2, and A3. As a result, the control signals PWBE0B through PWBE3B become (0, 0, 0, 0) so that the address signals RA0B1B through RA01 become (1, 1, 1, 1) to thereby activate all of the word lines WL0 through WLn. Inasmuch as the control signals PWBE0B through PWBE3B are at "low" logic values, the output signal PEQiB of the write and read control unit 107 is driven to a "low" logic value. Thus, the equalization transistors 1203a, 1203b, and 1203c of FIG. 12 are turned off to thereby allow the read operation.
Unfortunately, in a conventional integrated circuit memory device having a wafer burn-in test capability as described hereinabove, there may be a momentary interval during a wafer burn in test read operation in which the operation control signal or equalization signal PEQiB has not yet reached a "low" logic value. During this momentary interval the charge distribution of the memory cell may not be reliable when the word line is activated, which may cause the read operation to fail. Thus, a conventional integrated circuit memory device having a wafer burn-in test capability may be subject to the aforementioned race condition when performing a read operation because the read and write control unit 107 derives its inputs from the word line selection unit 105.